Coding styles for different RAM configurations (part-2)

Write first mode : most often user would like to see the same data at the output port which is being written during read-write conflict. Here’s the Verilog code to write a code, from RTL it should not be difficult to understand the behavior of the module.

Verilog coding style: 1

always @(posedge clk)
begin
         if (we)
             mem[addr] <= din;
end
always @(posedge clk)
begin
         if (we)
             dout <= din;
         else
             dout <= mem[addr];
end

conditional statement in the second ‘always’ block will create a 2:1 mux for dout with ‘we’ working as select line.

Fig2: RTL view for Single port write first -1

So what one needs to understand here is the point that Block RAM element in most of the FPGAs support write first mode internally and no glue logic is required to be created. Further some synthesis software are so intelligent that if the mode is not supported internally then they will create a glue logic and implement this functionality.

Verilog coding style: 2

always @(posedge clk)
begin
if (we)
mem[addr] <= din;
reg_addr <= addr;
end
assign dout = mem[reg_addr];


So now one can argue why I have discussed this coding style under 'write first' configuration mode. Here we have registered the read address but not the write address so it is straightforward that if the read and write operations are performed on location for one clock cycle then there will not be any conflict and dout will read from previous data. But if address is not changed for two or more number of clock cycles then read-write conflict will occur and that needs to be resolved and from RTL. It is clear that dout will read from the same address where write operation is happening in second and consequent clock cycles. Also note dout is not defined as 'reg' here.

Fig3: RTL view for Single port write first -2

cont...

Coding styles for different RAM configurations (part-1)

Sometime back I was very much confused about different configurations & modes that most of the block RAM architectures inside the FPGA support. So I thought why not compile all relevant information at one single point to help beginners and engineers for reference. First and foremost important pint to know is that at least either the read address or the output data in your RTL code (for RAM) should be registered in order to infer block RAM. Following are some of the possible configurations that an FPGA can support:

• Single port RAM
• Simple dual port RAM
• True dual port RAM
• RAM with initialization
• ROM

Except the last memory configuration (i.e. ROM), all others can further be configured in one of the following modes
• Read first mode
• Write first mode
• No change mode

These configuration modes make sense during state of conflict i.e. when user's code tries to write to as well as read from the same memory location in same clock cycle. In this situation, based on the RTL code, synthesis tool should implement it. Block RAM elements in some of the FPGAs support these modes internally (like Xilinx block RAM), whereas in other cases, some synthesis tools may facilitate the users to optionally implement the conflict resolving glue logic through available resources (LUTs & FFs).

Single port RAM (SPRAM): Out of these 5 configurations, Single port RAM is the easiest one with single address port for both read and write operations. I will start with this configuration mode first of all. In this configuration, conflict will occur every time when there is read as well write operations are performed in the same clock cycle.
Read First mode: During the state of conflict, output reflects the existing memory contents not the one which is being written into.

Verilog coding style:

always @(posedge clk)
begin 
if (we)
mem[addr] <= din;
end
always @(posedge clk)
begin
dout <= mem[addr];
end  

Here we have only output data registered, read address is not registered. So one can see every time, user writes into the RAM, conflict will occur as you are reading the same location as well, but if you are not writing into the memory then it's only a read operation and no conflict. So during should be resolved by either the Block RAM element internally or through glue logic. Some synthesis tools support this feature of creating glue logic to resolve the conflict. It is not as straight forward to create a glue logic for read first mode as it is for other cases. It is important to understand that what kind of behavior you implementation is going to provide you for this kind of coding style.

Fig 1: RTL view for Single port Read First RAM

 cont...

FPGA architecture

In the market, FPGA architectures are available in different kinds of flavors. They are available for small applications and low cost to high performance with large number of gates. There are some FPGAs, which tend to bring in unique feature of low power and small form factor which makes them suitable for high speed mobile applications.

Most of the FPGA architectures have following common basic elements internally:

• Configurable Functional Elements 
• Input/Output Element
• DSP Elements
• Block RAM Elements
• PLL Elements

Configurable Functional Elements (CFE) is the basic building element for FPGA architecture, it has the capacity to implement both combinatorial or sequential Boolean function. To implement the combinatorial function it contains multiple inputs Look Up Tables (LUTs) and flip flops to realize sequential Boolean function. it may also contains various multiplexers to provide selectivity.

Input/Output Element (IOE) provides the logic to configure an FPGA pin as input, output or inout mode. At the time of assigning IOs to ports of a designs, users can also opt for IO standard (LVCMOS33, LVCMOS25, LVTTL33 etc.), driving strength etc. for the pins. 

DSP Elements (DSPE) has become essential part of an FPGA today. The reason is market driven, today most of the applications require DSP engine to process data digitally which provides predictable quality of results and performance. All communication and mobile application require this feature and so FPGAs are provide this elements internally.

Block RAM Elements (BRAME) makes an essential part of any digital logic design. Multiple block RAM elements are used as large RAM block in variety of configurable modes. Mostly all FPGAs provides capability to configure them as ROM as well which is useful.

PLL Elements Most of the applications today require more than one CLOCK sources with different frequency in a design. PLL elements help generate precisely different frequencies and phase matched with source as well. In addition to this, PLL elements can provide variety of other features like fine/coarse phase delay, frequency multiplication/division etc.

Besides these basic elements, FPGA also provides global buffer elements for clocking sources and a dedicated clocking network to minimize clock skew as well. This helps users to concentrate more on designing rather than worrying about skew and fan out capability of clocks.

In the market today, FPGAs from following manufacturers are available in a broad variety:

• Xilinx
• Altera
• Actel
• Lattice
• Achronix
• Silicon Blue

Readers are encouraged to go to their website and explore more, in case of any questions or discussion please leave a comment.

FPGAs & designing with them

Field Programmable Gate Array (FPGA) devices have become very popular for digital logic design. Today variety of FPGA devices from different manufacturers are available in market to target specific application area. Their cost effectiveness as compared to ASICs manufacturing and increased avaliability of gates per area has made them further economic to be used for ASIC prototyping. Large number of ASIC designs are first prototyped with high end FPGA boards to reduce the time to market. It helps designers and verification engineers to start working well before the first ASIC gets ready.
My blogs on designing with FPGAs will discuss about the intricacies of different FPGA architectures and other common but important topics related to FPGA design.