FPGA design: Coding styles for different RAM configurations (part-1)

Sometime back I was very much confused about different configurations & modes that most of the block RAM architectures inside the FPGA support. So I thought why not compile all relevant information at one single point to help beginners and engineers for reference. First and foremost important pint to know is that at least either the read address or the output data in your RTL code (for RAM) should be registered in order to infer block RAM. Following are some of the possible configurations that an FPGA can support:

• Single port RAM
• Simple dual port RAM
• True dual port RAM
• RAM with initialization
• ROM

Except the last memory configuration (i.e. ROM), all others can further be configured in one of the following modes
• Read first mode
• Write first mode
• No change mode

These configuration modes make sense during state of conflict i.e. when user's code tries to write to as well as read from the same memory location in same clock cycle. In this situation, based on the RTL code, synthesis tool should implement it. Block RAM elements in some of the FPGAs support these modes internally (like Xilinx block RAM), whereas in other cases, some synthesis tools may facilitate the users to optionally implement the conflict resolving glue logic through available resources (LUTs & FFs).

Single port RAM (SPRAM): Out of these 5 configurations, Single port RAM is the easiest one with single address port for both read and write operations. I will start with this configuration mode first of all. In this configuration, conflict will occur every time when there is read as well write operations are performed in the same clock cycle.
Read First mode: During the state of conflict, output reflects the existing memory contents not the one which is being written into.

Verilog coding style:

always @(posedge clk)
begin
if (we)
mem[addr] <= din;
end
always @(posedge clk)
begin
dout <= mem[addr];
end

Here we have only output data registered, read address is not registered. So one can see every time, user writes into the RAM, conflict will occur as you are reading the same location as well, but if you are not writing into the memory then it's only a read operation and no conflict. So during should be resolved by either the Block RAM element internally or through glue logic. Some synthesis tools support this feature of creating glue logic to resolve the conflict. It is not as straight forward to create a glue logic for read first mode as it is for other cases. It is important to understand that what kind of behavior you implementation is going to provide you for this kind of coding style.