Coding styles for different RAM configurations (part-2)

Write first mode : most often user would like to see the same data at the output port which is being written during read-write conflict. Here’s the Verilog code to write a code, from RTL it should not be difficult to understand the behavior of the module.

Verilog coding style: 1

always @(posedge clk)
begin
         if (we)
             mem[addr] <= din;
end
always @(posedge clk)
begin
         if (we)
             dout <= din;
         else
             dout <= mem[addr];
end

conditional statement in the second ‘always’ block will create a 2:1 mux for dout with ‘we’ working as select line.

Fig2: RTL view for Single port write first -1

So what one needs to understand here is the point that Block RAM element in most of the FPGAs support write first mode internally and no glue logic is required to be created. Further some synthesis software are so intelligent that if the mode is not supported internally then they will create a glue logic and implement this functionality.

Verilog coding style: 2

always @(posedge clk)
begin
if (we)
mem[addr] <= din;
reg_addr <= addr;
end
assign dout = mem[reg_addr];


So now one can argue why I have discussed this coding style under 'write first' configuration mode. Here we have registered the read address but not the write address so it is straightforward that if the read and write operations are performed on location for one clock cycle then there will not be any conflict and dout will read from previous data. But if address is not changed for two or more number of clock cycles then read-write conflict will occur and that needs to be resolved and from RTL. It is clear that dout will read from the same address where write operation is happening in second and consequent clock cycles. Also note dout is not defined as 'reg' here.

Fig3: RTL view for Single port write first -2

cont...